The present invention relates to a method of forming an impurity region in a semiconductor device such as a CMOS type semiconductor integrated circuit device.
FIGS. 17(a)-17(c) and FIGS. 18(a), 18(b) are a process step diagram of a first prior art method of forming a source drain impurity region in the CMOS type semiconductor integrated circuit device. A gate electrode film 203 is formed on a surface of a semiconductor substrate 201 of a first conductivity type and on a surface of a well 202 of a second conductivity type opposite to the first conductivity type, in superposed relation to an underlying gate insulating film (FIG. 17(a)). Thereafter, a pair of gate electrodes 204 and 205 are concurrently patterned, respectively, on a first area into which the first conductivity type impurity is to be doped and on a second area into which the second conductivity type impurity is to be doped, by a first patterning process using a resist film 206. The unmasked remaining portion of the gate electrode film 203 is removed by etching process (FIG. 17(b)). Then, the second area into which the second conductivity type impurity is to be doped is masked by a second patterning process using a resist film 207. Subsequently the first conductivity type impurity is doped into the first area in in self-alignment manner through the gate electrode 204 to form a source drain impurity region 209 (FIG. 17(c)). In a similar manner, the first area is then masked by a third patterning process, and the second conductivity type impurity is doped into the second area to form another source drain impurity region 210 (FIG. 18(a)). Thus, a pair of two different conductivity types of transistors are formed as a CMOS pair (FIG. 18(b)).
FIGS. 19(a)-19(e) are a process step diagram of a second prior art method of forming an impurity region for device isolation in the CMOS type semiconductor integrated circuit device. A nitride film 211 is formed as an anti-oxidation film on a semiconductor substrate 201 of the first conductivity type and on a well 202 of the second conductivity type opposite to the first conductivity type, in superposed relation to an underlying pad oxide film (FIG. 19(a)). Thereafter, the nitride film 211 is selectively masked by a first patterning process using a photoresist film 214 over a first conductivity type device region 212 and over a second conductivity type device region 213. Then, the remaining unmasked portion of the nitride film 211 is removed by etching (FIG. 19(b)). After removing the photoresist 214, the second conductivity type device region 213 is masked by a second patterning process using a photoresist 215. Subsequently, a first conductivity type impurity is doped around the first device region 212 in self-alignment manner (FIG. 19(c)). In a similar manner, the first device region 212 is masked by a third patterning process, and a second conductivity type impurity is doped around the second device region 213 (FIG. 19(d)). By such a process, a pair of impurity regions 216, 217 are formed for device isolation of two different conductivity types of transistors which constitute a CMOS pair (FIG. 19(e)).
FIGS. 20(a), 20(b) and FIGS. 21(a)-21(c) are a process step diagram of a third prior art method of forming an impurity region for an electrical contact with a metal lead in the CMOS type semiconductor integrated circuit device. An insulating film 220 is formed over a surface of a semiconductor substrate 201 of the first conductivity type and over a surface of an impurity-doped well 202 of the second conductivity type opposite to the first conductivity type, so as to cover a first conductivity impurity region 218 which defines a source drain region and to cover a second conductivity impurity region 219 which defines another source drain region (FIG. 20(a)). Thereafter, the insulating film 220 is selectively masked by a first patterning process using a photoresist 223 to define a first inter-layer insulating section 221 and a second inter-layer insulating section 222. Then, the unmasked portion of the insulating film 220 is removed by etching to form contact holes (FIG. 20(b)). Then, after removing the photoresist 223, the second inter-layer insulating section 222 is selectively masked by a second patterning process using a photoresist 224, while a first conductivity type impurity is doped in self-alignment manner through the other inter-layer insulating section 221 to form high impurity density regions 225 in the source drain region 218 (FIG. 21(a)). In a similar manner, the first inter-layer insulating section 221 is masked by a third patterning process, while a second conductivity type impurity is doped to form other high impurity density regions 226 (FIG. 21(b)). By such processings, the two conductivity types of impurity regions 225, 226 are formed correspondingly to a CMOS pair of two different conductivity types of transistors so as to reduce an electric contact resistance to a metal lead pattern (not shown).
In the first prior art fabrication process, the gate electrode film such as a polysilicon film is etched through the first patterning process to form a pair of gate electrodes. Thereafter, the first area is selectively exposed by the second patterning process so as to dope the first conductivity type impurity to form the first impurity region. Subsequently, the second area is selectively exposed by the third patterning process so as to dope the second conductivity type impurity to form the second impurity region. In the second prior art fabrication process, the nitride film is selectively etched through the first patterning process to cover a pair of device regions. Thereafter, the second patterning process is carried out to selectively expose a surrounding area of the first device region so as to dope the first conductivity type impurity to form the first device isolation region. Lastly, the third patterning process is carried out to selectively expose another surrounding area of the second device region so as to dope the second conductivity type impurity to form the second device isolation region. In the third prior art doping method, the insulating film is etched selectively through the first patterning process to form contact holes which communicate with the source drain regions. The second patterning process is carried out to selectively open a first group of the contact holes so as to dope the first conductivity type impurity to form the first high impurity density region effective to reduce a contact resistance. Lastly, the third patterning process is carried out to selectively open a second group of the contact holes so as to dope the second conductivity type impurity to form the second high impurity density region effective to reduce a contact resistance. In these prior art doping methods, at least three steps of patterning are required in order to dope two different conductivity types of impurities.